8#include <botan/internal/noekeon.h>
10#include <botan/internal/cpuid.h>
11#include <botan/internal/loadstor.h>
12#include <botan/internal/rotate.h>
21inline void theta(uint32_t& A0, uint32_t& A1, uint32_t& A2, uint32_t& A3,
const uint32_t EK[4]) {
41inline void theta(uint32_t& A0, uint32_t& A1, uint32_t& A2, uint32_t& A3) {
56inline void gamma(uint32_t& A0, uint32_t& A1, uint32_t& A2, uint32_t& A3) {
73#if defined(BOTAN_HAS_NOEKEON_SIMD)
83#if defined(BOTAN_HAS_NOEKEON_SIMD)
95const uint8_t Noekeon::RC[] = {
96 0x80, 0x1B, 0x36, 0x6C, 0xD8, 0xAB, 0x4D, 0x9A, 0x2F, 0x5E, 0xBC, 0x63, 0xC6, 0x97, 0x35, 0x6A, 0xD4};
104#if defined(BOTAN_HAS_NOEKEON_SIMD)
107 simd_encrypt_4(in, out);
115 for(
size_t i = 0; i != blocks; ++i) {
121 for(
size_t j = 0; j != 16; ++j) {
123 theta(A0, A1, A2, A3, m_EK.data());
129 gamma(A0, A1, A2, A3);
137 theta(A0, A1, A2, A3, m_EK.data());
152#if defined(BOTAN_HAS_NOEKEON_SIMD)
155 simd_decrypt_4(in, out);
163 for(
size_t i = 0; i != blocks; ++i) {
169 for(
size_t j = 16; j != 0; --j) {
170 theta(A0, A1, A2, A3, m_DK.data());
177 gamma(A0, A1, A2, A3);
184 theta(A0, A1, A2, A3, m_DK.data());
195 return !m_EK.empty();
201void Noekeon::key_schedule(std::span<const uint8_t> key) {
207 for(
size_t i = 0; i != 16; ++i) {
209 theta(A0, A1, A2, A3);
215 gamma(A0, A1, A2, A3);
230 theta(A0, A1, A2, A3);
static bool has_simd_32()
size_t parallelism() const override
void encrypt_n(const uint8_t in[], uint8_t out[], size_t blocks) const override
std::string provider() const override
void decrypt_n(const uint8_t in[], uint8_t out[], size_t blocks) const override
bool has_keying_material() const override
void assert_key_material_set() const
void zap(std::vector< T, Alloc > &vec)
constexpr T rotl(T input)
void theta(SIMD_4x32 &A0, SIMD_4x32 &A1, SIMD_4x32 &A2, SIMD_4x32 &A3, const SIMD_4x32 &K0, const SIMD_4x32 &K1, const SIMD_4x32 &K2, const SIMD_4x32 &K3)
constexpr T rotr(T input)
constexpr auto store_be(ParamTs &&... params)
constexpr auto load_be(ParamTs &&... params)
void gamma(SIMD_4x32 &A0, SIMD_4x32 &A1, SIMD_4x32 &A2, SIMD_4x32 &A3)